Sr Asic Design Verification Engineer Uvm Ovm System Verilog Job In Na

ASIC Verification Engineer-UVM / OVM /System Verilog / Verilog / ASIC / FPGA

We are partnered up with a well-established Semiconductor organisation who specialize in ASIC and FPGA design and Verification services and custom IP development who are looking for Senior ASIC Verification Engineer to join their team in Canada.

If this is you please continue reading below!

Responsibilities:

• Prime the verification activities for a block or an entire chip.
• Develop verification environment architecture using UVM.
• Document test environment associations and write test cases.
• Support lab bring-up with direct test cases.
• Perform code and functional coverage.

Relocation and visa sponsorship is available

Qualifications:

• 8+ years of experience in ASIC verification.
• Highly skilled in Verilog, SystemVerilog,
• Significant experience with OVM/UVM methodologies.
• Experience with SONET, OTN, Ethernet, PCIe is a significant asset.

Keywords: UVM / FinFet /System Verilog / Verilog / Emulation / ASIC / FPGA

If interested Apply via LinkedIn, or send your CV to fm@eu-recruit.com

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