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THE ROLE:
The Display team within the GPU Technologies & Engineering(G&E) is hiring an Display IP Design Manager for the Display HUB blocks! The design is engineered to deliver efficient real time memory accesses to the display memory surfaces adhering to strict product power, performance and area metrics.
THE PERSON:
This is a unique opportunity for an experienced Leader to command a skilled team of Design and Verification Engineers to deliver solutions across AMD's dGPU, APU and Semi-custom business units. As a hands on Manager, you will be working with industry established top talents in the Display and Memory subsystem fields. A successful candidate should demonstrate experience leading large IP developments, motivated to meet program goals with a high quality bar and show solid technical decision making skills. Leadership experience should span across the full IP development phases - planning, architecture, design, verification, signoff and post silicon activities.
KEY RESPONSIBILITIES
PREFERRED EXPERIENCE:
ACADEMIC CREDENTIALS:
LOCATION:
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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