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Job Description
Job Title: Lead Design Verification Engineer (4 openings)Duration: FulltimeLocation: Vancouver, British Columbia, Canada (Onsite only)Experience: 8 to 15 yearsJob Description:Experience in SOC level verification.Experience in PCie or Nvme.Experience with SV-UVM methodology.Experience on developing testbench and all TB components.Experience on high-speed interface: PCIe, USB.System-on-a-chip verification with multiple CPUs and fixed function units with AXI or NOC interconnects.