Job Description
- Comprehend high-level requirements and translate them into detailed specifications.
- Develop and implement RTL (Register Transfer Level) logic, primarily using Verilog or System Verilog. This includes conducting block-level simulations, performing ASIC synthesis, and inserting DFT (Design for Testability) while achieving timing closure.
- Collaborate with cross-functional teams, including verification, design, hardware, and support teams.
- Conduct laboratory setup, product integration, and provide ongoing support.
- Offer technical assistance to customers and guide them through resolving complex technical issues.
Requirements
The ideal candidate for this role is a seasoned Senior/Staff/Principal IC Design Engineer with the following qualifications:
- A minimum of an undergraduate degree in Electrical Engineering (EE) or equivalent skills and experience.
- A minimum of 8+ years of progressively responsible experience in the field.
- Proficiency in modern ASIC development practices, including RTL logic design, synthesis, static timing analysis (STA), linting, and logic equivalence checking (LEC), along with a solid grasp of place and route (PnR) methodologies.
- Experience dealing with intricate asynchronous clock domains and high-speed serial interfaces.
- Practical experience in a lab environment, adept at troubleshooting issues up to the system level.
- Knowledge or hands-on experience with some of the following areas: GPUs and Display Interfaces, Multi-rate PCS (Physical Coding Sublayer), 10/25/40/100GbE (Gigabit Ethernet), Packet Processing, OTN (Optical Transport Network), Routers/Switches.
- Familiarity with industry-standard interfaces such as HDMI, DisplayPort, USB, Ethernet, PCIe, SPI, I2C, USB, AMBA, GPIO, SRIO (Serial RapidIO), DDR/SDRAM/DMA.
- Bonus points for experience in test verification and scripting.
- Proven track record as a self-starter, a team player, and a leader in the field.