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Job Description
A multinational technology company is seeking an experienced engineer in Toronto to develop RTL for SoC designs. The ideal candidate will have at least 3 years of experience in RTL design and implementation, as well as proficiency in Verilog or SystemVerilog. This role involves working closely with verification teams and integrating various blocks into a full chip design. The position offers a hybrid work model and a competitive salary range of CAD 109,380.00 – 154,420.00 annually. #J-18808-Ljbffr